![digital logic - is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop? - Electrical Engineering Stack Exchange digital logic - is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop? - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/DrYjD.png)
digital logic - is it possible to make asynchronous down counter modulo 6 with 3 JK flip-flop? - Electrical Engineering Stack Exchange
![17. The BCD (MOD10) synchronous up counter circuit constructed with D... | Download Scientific Diagram 17. The BCD (MOD10) synchronous up counter circuit constructed with D... | Download Scientific Diagram](https://www.researchgate.net/publication/319203501/figure/fig19/AS:529761929371659@1503316494668/The-BCD-MOD10-synchronous-up-counter-circuit-constructed-with-D-flip-flops.png)
17. The BCD (MOD10) synchronous up counter circuit constructed with D... | Download Scientific Diagram
![MOD 9 Synchronous Up Counter Using JK Flip Flop | Mod 9 Up counter | Counter using JK flip flop - YouTube MOD 9 Synchronous Up Counter Using JK Flip Flop | Mod 9 Up counter | Counter using JK flip flop - YouTube](https://i.ytimg.com/vi/IRLKuNKVc3k/maxresdefault.jpg)
MOD 9 Synchronous Up Counter Using JK Flip Flop | Mod 9 Up counter | Counter using JK flip flop - YouTube
![simulation - Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong - Electrical Engineering Stack simulation - Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong - Electrical Engineering Stack](https://i.stack.imgur.com/D02EU.png)
simulation - Trying to make a mod-10 counter with JK flip-flops in CircuitMaker but my outputs are always coming out HIGH instead of counting, not sure whats wrong - Electrical Engineering Stack
![In the modulo 6 ripple counter shown in the figure. the output of the 2 input gate is used to clear the J K flip flops.The 2 input gate is In the modulo 6 ripple counter shown in the figure. the output of the 2 input gate is used to clear the J K flip flops.The 2 input gate is](https://df0b18phdhzpx.cloudfront.net/ckeditor_assets/pictures/1594855/original_5.23-28.png)